Current Issue : July - September Volume : 2012 Issue Number : 3 Articles : 5 Articles
Nonuniform random numbers are key for many technical applications, and designing efficient hardware implementations of nonuniform\r\nrandom number generators is a very active research field. However, most state-of-the-art architectures are either tailored\r\nto specific distributions or use up a lot of hardware resources. At ReConFig 2010, we have presented a new design that saves up\r\nto 48% of area compared to state-of-the-art inversion-based implementation, usable for arbitrary distributions and precision. In\r\nthis paper, we introduce a more flexible version together with a refined segmentation scheme that allows to further reduce the\r\napproximation error significantly. We provide a free software tool allowing users to implement their own distributions easily, and\r\nwe have tested our random number generator thoroughly by statistic analysis and two application tests....
With the evolution of technology, the system complexity increased and the application fields of the embedded system expanded.\r\nCurrent applications need a high degree of performance, flexibility, and efficient development environments. Today, reconfigurable\r\nlogic allows to meet the on-chip processing requirements with new benefits resulting from partial and dynamic reconfiguration.\r\nBut the dimension introduced in the design of these systems requires more abstraction to manage their complexity and efficient\r\nmodels to provide reliable preliminary estimations. While classical multiprocessor systems can be modeled without difficulty, the\r\nuse of partial run-time reconfiguration in heterogeneous flexible system-on-chips is generally not covered. The contribution of\r\nthis paper is to address this with an extension of the AADL language able to model the reconfigurable logic, possibly considering\r\ndynamic reconfiguration and power consumption requirements. The proposed AADL model is divided into three levels to provide\r\na generic and hierarchical approach separating the static and dynamic parts of current FPGAs. These levels are exposed in detail\r\nand illustrated on a concrete example of FPGA device. The design space exploration of an application deployment using this model\r\nis also presented....
Parameterised reconfiguration is a method for dynamic circuit specialization on FPGAs. The main advantage of this new concept\r\nis the high resource efficiency. Additionally, there is an automated tool flow, TMAP, that converts a hardware design into a more\r\nresource-efficient run-time reconfigurable design without a large design effort. We will start by explaining the core principles\r\nbehind the dynamic circuit specialization technique. Next, we show the possible gains in encryption applications using an AES\r\nencoder. Our AES design shows a 20.6% area gain compared to an unoptimized hardware implementation and a 5.3% gain\r\ncompared to a manually optimized third-party hardware implementation. We also used TMAP on a Triple-DES and an RC6\r\nimplementation, where we achieve a 27.8% and a 72.7% LUT-area gain. In addition, we discuss a run-time reconfigurable DNA\r\naligner.We focus on the optimizations to the dynamic specialization overhead. Our final design is up to 2.80-times more efficient\r\non cheaper FPGAs than the original DNA aligner when at least one DNA sequence is longer than 758 characters. Most sequences\r\nin DNA alignment are of the order 213....
By means of partial reconfiguration, parts of the hardware can be dynamically exchanged at runtime. This allows that streaming\r\napplication running in different modes of the systems can share resources. In this paper, we discuss the architectural issues to design\r\nsuch reconfigurable systems. For being able to reduce reconfiguration time, this paper furthermore proposes a novel algorithm to\r\naggregate several streaming applications into a single representation, called merge graph. The paper also proposes an algorithm to\r\nplace streaming application at runtime which not only considers the placement and communication constraints, but also allows to\r\nplace merge tasks. In a case study, we implement the proposed algorithm as runtime support on an FPGA-based system on chip.\r\nFurthermore, experiments show that reconfiguration time can be considerably reduced by applying our approach....
Xilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous global clock nets to\r\nsupport high-speed mixed frequency designs. Digital Clock Managers in combination with Global Clock Buffers are already in\r\nplace to generate the desired frequency and to drive the clock networks with different sources, respectively. Currently, almost all\r\ndesigns run at a fixed clock frequency determined statically during design time. Such systems cannot take the full advantage of\r\npartial and dynamic self-reconfiguration. Therefore, we introduce a new methodology that allows the implemented hardware to\r\ndynamically self-adopt the clock frequency during runtime by reconfiguring the Digital ClockManagers.We also present a method\r\nfor online speed monitoring which is based on a two-dimensional online routing. The created speed maps of the FPGA area can be\r\nused as an input for the dynamic frequency scaling. Figures for reconfiguration performance and power savings are given. Further,\r\nthe tradeoffs for reconfiguration effort using this method are evaluated. Results show the high potential and importance of the\r\ndistributed dynamic frequency scaling method with little additional overhead....
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